Chipmaker GlobalFoundries (GF) and semiconductor IP organization Arm say they’ve done the design and style for a test silicon 3D chip using technological innovation capable of producing a million 3D connections for each square millimeter. Their technological know-how binds two wafers of chips with each other with densely packed vertical copper hyperlinks. The firms see it as a route to boosting the motion of information for programs this kind of as machine mastering, and to enabling the integration of various systems this sort of as RF and silicon photonics.
“We’ve carried out lots of a long time of hypothetical investigation into what we can do in just Arm IP when interconnect density receives substantial ample,” says Greg Yeric, investigate fellow at Arm, in Austin, Texas. The firm predicted that after 3D connections could be created 10 micrometers apart or significantly less, designers would be ready to use 3D connections to shorten the “critical path” in a processor core. That is the path that makes the longest signal hold off and as a result limitations functionality. The vertical connections enable the important route to be folded up to stream from just one silicon die to the other. GF’s technologies has now reached that threshold.
Facial area-to-confront wafer-to-wafer bonding requires signing up for ICs collectively at the top rated of the interconnect levels [gray] previously mentioned the silicon transistors. Just one wafer has by means of silicon vias that lead to bumps [top], which are made use of to connect the chip to its bundle.
The technological know-how is named “face-to-face” wafer-to-wafer bonding. Utilizing this technique, the method is designed in two components and constructed on two wafers. 1 of the wafers contains vertical connections called by way of-silicon vias (TSVs) that increase down some length into the physique of the silicon. As regular in CMOS engineering, the interconnects that bind the transistors into circuits are designed in many layers earlier mentioned the silicon, but for wafer-to-wafer bonding, the major layer consists of a dense array of bonding websites. The wafers are meticulously aligned and bonded with each other deal with to deal with. Then enough of the silicon is removed from the back aspect of the wafer with the TSVs so that people connections are exposed. The 3D chips are then diced up and packaged.
The take a look at chip the two corporations have now built is intended, 1st, to determine how nicely Arm’s mesh interconnect technological know-how performs in 3D. This will allow them to nail down a set of metrics for products enhancement teams. They’ll be screening the silicon in early 2020.
Both equally GF and Arm engineers concur that the most complicated element of having to this position was the absence of electronic layout automation (EDA) tools able of this kind of 3D design. The crew has been doing the job with Ga Tech professor Sung Kyu Lim to allow 3D designs utilizing 2D EDA tools. They’re also functioning with EDA software makers, which Yeric would not identify.
Hybrid bonding joins copper connections between wafers.
Adding to the layout complexity, the group attempted to integrate IEEE’s draft “design for test” typical (IEEE p1838). Arm and GlobalFoundries want to be capable to take a look at the dies on the wafers equally before and right after bonding to guarantee a fantastic generate of performing 3D chips. Substantially of this job “was an effort towards having the structure ecosystem all set,” states Arm principal research engineer Saurabh Sinha.
“Our target in this article is to help providers like Arm, and other consumers, to be capable to scale to higher volume at the time the applications are in the resource box,” claims John Pellerin, chief technologist, platforms, and vice president for all over the world R&D at GlobalFoundries.
This publish was corrected to give the suitable titles of Greg Yeric and John Pellerin.